Principal Engineer Digital Design
vor 2 Wochen
At the Forefront of Digital Innovation
We are seeking a highly skilled Digital Design Engineer to join our cutting-edge team in Graz, Austria.
As a vital component in the evolution of Battery Management System (BMS) and Power Management Integrated Circuit (PMIC) technology, you will play a pivotal part in crafting the next generation of BMS and PMIC technology.
The role involves taking on various responsibilities, including end-to-end digital circuit design and verification, defining architecture and hardware requirements, technical leadership and team management, DFT and functional safety compliance, and collaboration with cross-functional teams.
Key Responsibilities:- End-to-End Digital Circuit Design & Verification: Lead the entire RTL design process, from block-level to top-level, ensuring robust logic synthesis, static timing analysis, and seamless integration across clock domains.
- Defining Architecture & Hardware Requirements: Translate product requirements into hardware specifications, working with system concept engineers to define optimal architectures and interfaces for digital modules.
- Technical Leadership & Team Management: Plan and execute digital design activities, oversee quality inspections, provide post-silicon bring-up support, and mentor a growing team of designers and students.
- DFT & Functional Safety Compliance: Lead design-for-test (DFT) efforts, including scan insertion and ATPG, while ensuring compliance with ATV ISO 26262 standards for functional safety.
- Collaborate with System, Verification & Chip Integration Teams: Work closely with cross-functional teams to define hardware architectures, review verification plans, and develop test cases that achieve high coverage.
- Pre-Silicon Verification & Quality Assurance: Analyze clock domain crossings (CDC) and linting, review pre-silicon verification plans, and ensure designs meet rigorous quality and testing standards.
- University degree (MSc) in Electrical Engineering, Computer Science, or a related field.
- 8+ years of hands-on experience in RTL digital design, including top-level integration of complex SoCs (Analog on Top or Digital on Top).
- Strong proficiency in RTL design using Verilog and SystemVerilog.
- Skilled in industry-standard tools like Excelium and Spyglass, with experience using UPF to manage power intent in design.
- Competent in scripting languages such as Python, Perl, and Tcl, along with medium-level experience in behavioral modeling.
- Proficient in design version control systems, including Perforce, ClearCase, SVN, and GIT.
- Fluency in English is essential, and knowledge of German is a plus.
- Extensive experience in Digital-On-Top integration and close interaction with Digital Backend teams.
- Proven track record working within Infineon's design environment and methodologies.
- Proficiency in formal verification using Jasper Gold or OneSpin, with expertise in ASIL ISO 26262 functional safety standards.
- Skilled in PrimeTime static timing analysis (STA), ATPG, and netlist generation.
- Experience in automating design documentation processes and improving documentation flows.
- Basic experience with SystemVerilog and UVM.
This position is subject to the collective agreement for workers and employees in the electrical and electronics industry. The monthly salary is paid 14 times per year, and a higher payment is negotiable depending on your expertise and skills. Infineon also offers additional employee benefits.
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