Senior ASIC Design Engineer for 5G NR PHY

vor 1 Monat

Dresden, Österreich Hays Teilzeit
  • Taking part in all aspects of digital design, from architecture and specification to RTL design and verification, for our 5G NR modem baseband PHY
  • Implementing baseband processing modules in RTL, and developing complex signal processing blocks, control mechanisms, and more 
  • Developing test plans and conducting functional verification, static timing analysis (STA), and FPGA development
  • Utilizing your knowledge of Verilog, RTL experience, and backend tools to create successful design implementations.
    • In-depth knowledge of the ASIC design flow, including RTL experience
    • Strong experience in complex ASIC design, with a focus on high performance and low power
    • Proficiency in DSP hardware implementations, including data path and control logic
    • Expertise in RTL design using Verilog.
    • Familiarity with LTE/5G NR standards 
    • Experience with ASIC design tools for simulation, debugging, synthesis, and timing analysis.
    • Knowledge of C/C++/systemC and python
    • Proficient in design methodologies and EDA tools for Lint, DFT, CDC, Synthesis, STA, and backend
      • Long term engagememt
      • Hybrid model: Dresden und remote Our many years of recruitment experience and our expert knowledge of the engineering job market make us a strong partner for engineers and technicians. We maintain close relationships with customers across all industries and therefore can provide engineering specialists with exciting projects and attractive job opportunities, drawing on your personal interests and experience. As your professional companion, we support you throughout the entire process, from the first contact to the first day on your new job – all this completely free of charge. Register now and look forward to many interesting and suitable positions and projects.

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