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Senior Verification Enigneer
vor 2 Wochen
- Specialised ASIC Design House
- West Austria A successful chip design house in Austria is looking to hire a Senior Verification Engineer to join their international team.
You will have the opportunity to work on complex and challenging projects working closely with the other teams in Europe.
Key Skills:
Experience in UVM.Having worked on a number of successful and complex ASIC projects.
Knowledge of a programming language (Verilog or SystemVerilog).An understanding of RTL design.
Fluent in English.
If you are interested in applying, or would like to find out more, please contact Lucy Edmondson.
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