Design Verification Internship
Vor 6 Tagen
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Smart people and inspiring, innovative technologies are the norm here. Do you love working on challenges that no one has solved before? Are you ready to be part of a team transforming wireless technology? Join us to help deliver the next groundbreaking Apple product. In this role, you will be a key member of our team in Linz or Munich working on the digital development for radio frequency (RF) transceivers. As part of the design verification team, you will collaborate closely with the RTL design implementation and systems teams to ensure highest quality design for sign-off.
**Description**
With mentorship, you will closely collaborate and engage with members of cross-functional disciplines including design, verification, and validation teams to experience what it takes to build a RF IC. Your work could include: - Verifying IP compliancies to specification - Defining chip-level verification plans to ensure coverage of specified features - Active participation in multi-functional collaboration with design teams to ensure a successful chip delivery - Execution of verification plans, analysing the results and debugging the design - Development of behavioural/functional models for sub-blocks and use them for design verification, gaining algorithmic knowledge.
**Minimum Qualifications**
- Currently enrolled in a Bachelor’s, Master’s or PhD degree program in Electrical Engineering, Computer Science, Information Technology or equivalent.
- Fluent English skills
- Eagerness to learn new things and take up new challenges
**Preferred Qualifications**
- Coursework focusing on microelectronics and IC design
- Understanding of digital design development technologies and/or embedded systems
- Strong analytical and problem solving skills
- Familiarity with state-of-the art verification methodologies, e.g. UVM, Formal Verification or Data Analysis
- Familiarity with C/C++, Verilog, SystemVerilog is a plusKnowledge of a scripting language is desirable (TCL, Python, Bash, or Perl)
Lebenslauf senden
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