cad drc

7 cad drc Stellenangebote in Österreich. Täglich aktualisierte Angebote.


  • Villach, Kärnten, Österreich Infineon Technologies Austria AG Vollzeit € 65.000 - € 95.000 Vertrag

    Infineon Technologies Austria AG in Austria seeks a Senior Layout Engineer to lead full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components. You will optimize layouts, verify with DRC/LVS/ERC, and manage parasitics to ensure power and signal integrity.The role requires 5+ years in CMOS/FinFET technologies, strong CAD...


  • Wernberg, Carinthia, Österreich Infineon Technologies Austria AG Vollzeit

    Infineon Technologies Austria AG in Austria seeks a Senior Layout Engineer to lead full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components.Bewerben Sie sich schnell, um Ihre Chancen auf ein Vorstellungsgespräch zu erhöhen Lesen Sie die vollständige Stellenbeschreibung unten.You will optimize layouts, verify with...


  • Premstätten, Steiermark, Österreich ams OSRAM Vollzeit € 90.000 - € 130.000 Vertrag

    Job descriptionDevelop and maintain Synopsys IC Validator (ICV), Siemens Calibre, Cadence PVS rule decks for Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), and antenna verification across multiple semiconductor technologiesExecute physical signoff verification flows using Synopsys IC Validator, Simens Calibre,...


  • Vasoldsberg, Steiermark, Österreich ams OSRAM Vollzeit

    Job description * Develop and maintain Synopsys IC Validator (ICV), Siemens Calibre, Cadence PVS rule decks for Design Rule Checking (DRC), Layout Versus Schematic (LVS), Electrical Rule Checking (ERC), and antenna verification across multiple semiconductor technologies * Execute physical signoff verification flows using Synopsys IC Validator, Simens...


  • Villach, Kärnten, Österreich Infineon Vollzeit

    Infineon Technologies Austria AG in Austria seeks a Senior Layout Engineer to lead full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components. You will optimize layouts, verify with DRC/LVS/ERC, and manage parasitics to ensure power and signal integrity. The role requires 5+ years in CMOS/FinFET technologies, strong CAD...