AMS Design Validation Engineer
Vor 2 Tagen
About the Job:
We are looking for a skilled AMS Design Validation Engineer to join our team at Apple Inc. in Munich, Germany. As a member of our team, you will be responsible for designing and implementing verification environments for mixed-signal designs.
Your Responsibilities:
- Design and implement verification environments using SystemVerilog and UVM
- Collaborate with Analog and Digital Design engineers to ensure bug-free tape-outs
- Develop and deliver test scenarios and assertions for pre-silicon verification
About You:
- You have a strong background in electrical engineering and computer science
- Hands-on experience with constraint random verification environments
- Knowledge of Object Oriented Programming (OOP)
The Ideal Candidate:
- Master's degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
- Hands-on experience with assertion based verification
- Familiarity with system design using C++, Python, or Verilog
- Familiarity with FPGA emulation platforms
About Our Offer:
We offer a competitive salary range of €80,000 - €110,000 per year, depending on your qualifications and experience. You will also have the opportunity to work on cutting-edge projects and collaborate with talented professionals from around the world.
What We Look For:
- Demonstrated expertise in design verification and validation
- Strong problem-solving skills and attention to detail
- Excellent communication and collaboration skills
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