Mixed Signal Design Verification Engineer Leader
vor 2 Wochen
We are looking for a talented Mixed Signal Design Verification Engineer to join our team in Munich. As a member of our team, you will work closely with Analog and Digital Design engineers to craft upcoming products that will delight and encourage millions of Apple's customers every single day.
The responsibilities include:
- Defining and designing self-checking verification environments for multi-layer systems using the SystemVerilog UVM library
- Executing verification tasks to ensure bug-free tape-outs
- Collaborating with the AMS DV team to improve verification techniques and tools for mixed-signal systems
This is a great opportunity to work with a talented team of engineers and contribute to the development of innovative products.
Minimum Qualifications
- Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
- Hands-on experience with constrained random verification environments
- Bachelor's degree in Electrical/Computer Engineering or related field
Estimated Salary: $110,000 - $140,000 per year
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