Innovative Mixed-Signal Verification Expert
Vor 2 Tagen
At Apple, we strive to create innovative products that transform people's lives. As a Design Verification Engineer in our Munich team, you will have the unique opportunity to craft cutting-edge mixed-signal designs that delight millions of Apple's customers worldwide.
About the RoleThis role involves designing and verifying complex verification environments for multi-layer systems using SystemVerilog UVM library. Your responsibilities will include:
- Construction of verification environments
- Coding of test scenarios and assertions
- Closely collaborating with Analog and Digital Design engineers
Your focus will be on creating bug-free first silicon for our mixed-signal designs. You will go beyond standard verification techniques by incorporating performance-based analysis, power-related analysis, and scenario design for early power estimation. Additionally, you will deliver tests for design and test engineering teams, perform gate-level verification (power and timing), and provide lab bring-up support.
Key ResponsibilitiesYou will be part of a dynamic team focused on research and innovations to improve verification techniques and tools for mixed-signal systems, increasing efficiency and quality. Key tasks include:
- Defining verification strategies and executing verification tasks
- Designing self-checking verification environments for multi-layer systems
- Delivering tests for design and test engineering teams
- Laboratory bring-up support
To succeed in this role, you should have:
- Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
- Hands-on experience with constrained random verification environments
- Basic design background to analyze verification results
- Proficiency in English language
While not mandatory, having the following skills will make you an even more attractive candidate:
- Masters degree or PhD in Electrical/Computer Engineering or equivalent industrial experience
- Familiarity with Assertion Based Verification
- Experience with system design using C++, Python, or Verilog
- Familiarity with FPGA emulation platforms
The minimum salary for this position is $79,204 gross per year for full-time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.
About AppleApple is an Equal Opportunity Employer committed to diversity and inclusion. We offer a competitive compensation package, opportunities for growth and development, and a work environment that fosters collaboration and innovation.
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